This application is related to U.S patent application Ser. No. 07/170,399, filed Mar. 18, 1988, entitled Context Switching Method and Apparatus for Use in a Vector Processing System, by D. Bhandarkar et al.; U.S. patent application Ser. No. 07/170,393, filed Mar. 18, 1988, entitled Exception Reporting Mechanism for a Vector Processor, by D. Bhandarkar et al.; and U.S. patent application Ser. No. 07/170,367, filed Mar. 18, 1988, entitled Method and Apparatus for Handling Asynchronous Memory Management Exceptions by a Vector Processor, by F. McKeen et al.
The invention relates to data processing system generally, and specifically to such data processing systems which are capable of executing vector instructions.
Certain high performance data processing systems include, in addition to a main or scalar processor, a separate vector processor to process vector instructions quickly and efficiently. Vector instructions direct a processor to perform memory, arithmetic or logical operations on data represented as vectors. The main or scalar processor processes the other type of instructions, called "scalar" instructions. Scalar instructions, for example, direct a processor to perform memory, arithmetic, or logical operations on logical or scalar data.
Vector instructions may include vector as well as scalar values as operands. Consequently vector instructions may have several different instruction formats depending upon the type of instruction, whether the instruction requires a scalar operand as well as vector operands, etc. The operands may be subject to different types of addressing, such as base-displacement addressing, which also affects the instruction formats.
Vector instructions processed by the IBM System/370 may be packed in a QST format, which has an operation code followed by a scalar register number, a first general register number, a vector register number, and a second general register number. The VV format, also used by the IBM System/370 has an opcode followed by three vector register numbers. These instruction formats require the main or scalar processor to be cognizant of the structure of the vector processor. For example, the scalar processor must be aware of how many vector registers the vector processor has. Unique formats for vector instructions also lead to increased complexity in the design of the scalar processor.
It is sometimes desirable to process only certain elements of a vector resulting from a logical or arithmetic operation. The general term for such selective vector processing is "masking." The IBM System/370 executes some classes of vector instructions under vector mask mode control. Vector mask mode control enables certain elements of the vector resulting from an operation to be "masked out." When the vector mask mode is off, the vector instruction operands are processed normally. When the vector mask mode is on, however, results are recorded only for elements which correspond to "ones" in a vector mask register. Elements corresponding to "zeros" remain unchanged.
Because the IBM System/370 requires that the mask register enabling bit be a "one," it cannot accommodate a program which uses negative logic in which a "zero" is the enabling value. In such a case, it would be preferable to be able to choose between a "one" or a "zero" being the enabling value.